This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-191979, filed Jun. 25, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a mounting technique of a semiconductor chip, particularly to a laminated structure of semiconductor chips on chip-mounting substrates in a laminated module in which a plurality of semiconductor chips are laminated, and a peripheral structure of the chips and the chip-mounting substrates.
2. Description of the Related Art
A semiconductor device constituted by laminating a plurality of semiconductor chips (semiconductor elements) is called a laminated semiconductor module, or a laminated semiconductor device. For example, a semiconductor chip constituted by laminating a plurality of memory chips is called a memory laminate. In general, when a number of semiconductor chip of one type are laminated as a memory laminate, external connection terminals for connecting each layers of semiconductor chip to other semiconductor chips are disposed at substantially the same positions on each layer. Therefore, since electric connection among the respective layers of the semiconductor chips can be constituted as substantially the same wiring constitutions among the layers, only small problems are generated in arranging the wiring.
In recent years, there has been an increasing demand for a compact-size semiconductor device. Therefore, as shown in FIG. 7, during manufacturing of a laminated semiconductor device 101, it has been necessary to mount (package) a chip 103 on a substrate 102 so that the center C of the semiconductor chip 103 agrees with the center X of the chip-mounting substrate (packaged substrate) 102. Additionally, it has been necessary to dispose and laminate the plurality of substrates 102 with the chips 103 mounted thereon so that the center C of the chip 103 and the center X of the substrate 102 substantially agree with a center Z of the whole device package 101.
Moreover, in recent years, semiconductor chips have been designed so that as many terminals as possible, such as electrodes, are disposed. For example, the chip 103 is formed with a substantially quadrangular shape in plan view, and a plurality of terminals 104 are densely arranged in each edge of one main surface of the chip. Furthermore, in a portion on which the chip 103 of the substrate 102 is mounted, pads 107 directly and electrically connected to the terminals 104 are disposed in a substantially quadrangular frame shape so that the pads have a one-to-one correspondence with the terminals 104. Additionally, in the substrate 102, a plurality of via terminals 105 individually and electrically connected to the terminals 104 via the pads 107 are densely arranged in a substantially quadrangular frame shape so as to surround the arrangement of the pads 107 from the outside in the vicinity of the pads. Each pad 107 is electrically connected beforehand to the via terminal 105 via a wiring 106 in one-to-one connection. Each wiring 106 is wired based on a predetermined wiring rule (design rule).
The chip 103 is mounted on the substrate 102 so that the terminal 104 is electrically connected to the pad 107, for example, by a flip chip method. Thereby, each terminal 104 is electrically connected to the via terminal 105 disposed opposite each edge of the chip 103 via the pad 107 and wiring 106. In this state, respective edges of the chip 103 are substantially parallel to portions corresponding to four frame edges formed of the arrangement of the via terminals 105.
Another laminated semiconductor device is a composite laminated semiconductor module (block module) 101 constituted by disposing the chips 103 whose types differ with the respective layers. In general, the outer shape, number of terminals 104, and mounted position of the chip 103 differ with the type of chip. Accordingly, the outer shape, number and mounted positions of pads 107 of the substrate 102 differ with the type of chip 103. When the respective chips 103 are electrically connected to one another among the layers of the composite laminated semiconductor module 101, an interlayer connecting wiring (not shown) other than the wiring 106 needs to be disposed in the module 101.
Additionally, the respective via terminals 105 are densely arranged so as to surround the portion on which the chip 103 with the pad 107 disposed therein is mounted from the outside in the vicinity of the portion. Moreover, most of the via terminals 105 are wired to the pads 107 arranged substantially opposite to the arrangement of the via terminals 105 so that the length of the wiring 106 becomes as short as possible. Therefore, it is remarkably difficult to simply wire the chips 103 of different layers to one another with a minimum distance. Furthermore, when the chips 103 of different layers are wired to one another, the wiring pattern on each substrate 102 includes a mixture of the wirings 106 arranged at coarse intervals, as shown by the two-dot chain line portion L in FIG. 7, and the wirings 106 arranged at dense intervals, as shown by the dotted portions H in FIG. 7. There is a possibility that such a wiring state (wiring pattern) conflicts with the wiring rule.
Therefore, in order to arrange the wirings among the layers in the module 101 without conflicting with the wiring rule, it is usually necessary to enlarge the size of the substrate 102 and broaden the interval between the via terminals 105. Then, the package size of the whole module 101 which was originally intended to be compact, disadvantageously increases.
According to one aspect of the present invention, there is provided a laminated-chip semiconductor device comprising: a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion; and a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.
Moreover, according to one aspect of the present invention, there is provided a laminated-chip semiconductor device comprising: a plurality of semiconductor chips having a plurality of terminals; and a plurality of chip-mounting substrates on each of which at least one of the semiconductor chips is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals in at least one of two or more laminated layers.
Furthermore, according to one aspect of the present invention, there is provided a laminated-chip semiconductor device comprising: a plurality of semiconductor chips having a plurality of terminals; and a plurality of chip-mounting substrates on each of which at least one of the semiconductor chips is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of another semiconductor chip in at least two predetermined layers among two or more laminated layers.
Additionally, according to one aspect of the present invention, there is provided a laminated-chip semiconductor device comprising: a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion; and a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a side edge rotated by a predetermined angle from a mutual parallel state with respect to an arrangement opposite to the side edge of the semiconductor chip in a whole arrangement of the relay terminals.
Moreover, according to one aspect of the present invention, there is provided a laminated-chip semiconductor device comprising: a plurality of semiconductor chips having a plurality of terminals; and a plurality of chip-mounting substrates on each of which at least one of the semiconductor chips is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a side edge rotated by a predetermined angle from a mutual parallel state with respect to an arrangement opposite to the side edge of the semiconductor chip in a whole arrangement of the relay terminals in at least one of two or more laminated layers.
Furthermore, according to one aspect of the present invention, there is provided a laminated-chip semiconductor device comprising: a plurality of semiconductor chips having a plurality of terminals; and a plurality of chip-mounting substrates on each of which at least one of the semiconductor chips is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a side edge rotated by a predetermined angle from a mutual parallel state with respect to at least two predetermined layers among two or more laminated layers.
Additionally, according to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip; one or a plurality of chip-mounting substrates on which at least one semiconductor chip is mounted, and which is constituted by laminating one to three layers along a thickness direction; and at least one pair of packaging members which are formed of predetermined materials and which are disposed around the semiconductor chip mounted on at least one layer of the chip-mounting substrate among the semiconductor chips mounted on the layers of the chip-mounting substrates so as to be symmetric with each other with respect to the semiconductor chip in the layer with the semiconductor chip disposed therein.
Moreover, according to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip; one or a plurality of chip-mounting substrates on each of which at least one semiconductor chip is mounted, and each of which is constituted by laminating one or a plurality of layers along a thickness direction; and at least three pairs of packaging members which are formed of predetermined materials and which are disposed around the semiconductor chip mounted on at least one layer of the chip-mounting substrate among the semiconductor chips mounted on the layers of the chip-mounting substrates so as to be symmetric with one another with respect to the semiconductor chip in the layer with the semiconductor chip disposed therein.